1. Field of the Invention
The present invention relates to a variable delay circuit built in a semiconductor device and a delay time setting method for the variable delay circuit, and particularly relates to a variable delay circuit having a reduced number of elements and a reduced chip area and a delay time setting method for the variable delay circuit.
2. Description of the Related Art
A conventional variable delay circuit is described in, for example, Japanese Patent Unexamined Application Publication No. 9-46195 (to be referred to as "Publication 9-461951, " hereinafter). FIG. 1 is a circuit diagram showing the conventional variable delay circuit described in the Publication 9-46195 and FIG. 2 is a circuit diagram showing the structure of a transfer gate shown in FIG. 1.
In the conventional variable delay circuit described in the Publication 9-46195, (n+1) (where n is an integer equal to 1 or higher) inverters I1, I2, . . . and In+1are connected in series as shown in FIG. 1. The output resistance is almost constant among the inverters I1, I2, . . . and In+1. Transfer gates S1, S2, S3, . . . and Sn and capacitive elements C1, C2, C3, . . . and Cn are connected in series between the nodes of adjacent inverters and a ground potential, respectively. The capacity is almost constant among the capacitive elements C1, C2, C3, . . . and Cn. The variable delay circuit is also provided with a selection circuit section 101 having output terminals D1, D2, D3, and . . . Dn. The output terminals D1, D2, D3, . . . and Dn are connected to the control terminals of the transfer gates S1, S2, S3, . . . and Sn, respectively. A controlling signal (binary code signal) indicating the number of transfer gates S1, S2, S3, . . . and Sn to be simultaneously turned on is inputted to the input terminal of the selection circuit section 101.
Each transfer gate is provided with a P-channel MOS transistor Q103 and an N-channel MOS transistor Q102 as shown in FIG. 2. An inverter IV102 is connected between the control terminal and the gate of the P-channel MOS transistor Q103. The binary signal inputted to the control terminal is, therefore, inputted to the gate of the N-channel MOS transistor Q102 as it is, and inputted to the P-channel MOS transistor Q103 after being inverted. In this way, the on/oft controlling of the P-channel MOS transistor Q103 and the N-channel MOS transistor Q102 is conducted.
In the conventional variable delay circuit constituted as stated above, if the value of n is 3, since output resistances R1, R2, R3 and R4 of the inverters I1, I2, I3 and I4, respectively, are almost constant and the capacities of the capacitive element C1, C2, C3 and C4 are almost constant, delay time Trc determined by a time constant .tau.=RC is almost constant, as well. The capacity of the capacitive element is set quite small and the output resistance R is set at about 100.OMEGA. so as to satisfy the relationship represented by (delay time Trc)&lt;&lt;(propagation delay time Tin of inverter). Thus, the delay time between {(n+1).times.Tin} and {(n+1).times.Tin+n.times.Tc} can be arbitrarily adjusted with a delay time Trc as a minimum unit. Although Tc is considered to be defined as the propagation delay time of a capacitive element, Publication 9-46195 makes no mentions thereof.
Nevertheless, the above-stated conventional variable delay circuit is provided with the transfer gates controlling the connection between capacitive elements and the ground respectively in addition to the series connected inverters and the capacitive elements connected between the output terminals of the inverters and the ground potential, respectively. Due to this, enormous number of transfer gate elements are provided in a circuit designed to process address signals, data input signals and the like and requiring many variable delay circuits which function to adjust delay time. As a result, the area of a chip incorporating such variable delay circuits disadvantageously increases.